library IEEE;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity alu is
	port(
		a		:	in	std_logic_vector(31 downto 0);
		b		:	in	std_logic_vector(31 downto 0);
		control	:	in	std_logic_vector(2 downto 0);
		result	:	out	std_logic_vector(31 downto 0);
		zero	:	out	std_logic
	);
end alu;

architecture alu_arch of alu is

	signal output : std_logic_vector(31 downto 0);

begin

	process(a, b, control) begin

		case control is
			when "000" => output <= (a and b);
			when "001" => output <= (a or b);
			when "010" => output <= (a + b);
			when "110" => output <= (a - b);
			when "111" =>
				if (a < b) then
					output <= x"00000001";
				else
					output <= (others => '0');
				end if;
			when "100" => output <= b(15 downto 0) & x"0000";
			when others => output <= (others => '0');
		end case;

	end process;

	zero	<= '1' when output = x"00000000" else '0';
	result	<= output;

end alu_arch;
